1. Field of the Invention
This invention relates to a semiconductor device comprising an IIL (or I.sup.2 L, intergrated injection logic) integrated with a vertical npn transistor and a vertical pnp transistor, and a method for its fabrication.
2. Description of the Prior Art
Conventional semiconductor devices can be exemplified by what is disclosed in Japanese Laid-open Patent Application No. 59-141261.
In FIG. 9, reference numeral 1 denotes a p-type semiconductor substrate; and 5, part of the emitter region of the IIL, which is an n.sup.+ -type buried layer formed at the same time as a collector buried layer (not shown) of a vertical npn transistor. Reference numeral 6 denotes part of a separating region, which is a p.sup.30 -type buried layer formed at the same time as a collector buried layer (not shown) of a vertical pnp transistor. Reference numeral 9 denotes an n.sup.- -type epitaxial layer formed on the p-type semiconductor substrate 1 embracing the n.sup.30 -type buried layer and the p.sup.+ -type buried layer 6, and 10 and 12 denote part of the separating region and part of the base region of the IIL, respectively, which are p.sup.- -type diffused layers formed at the same time as the collector region (not shown) of the vertical pnp transistor. Reference numeral 14 denotes an n.sup.+ -type diffused layer that constitutes an emitter lead-out portion of the IIL, and 17 and 18 denote an injector and part of the base region, respectively, of the IIL, which are p-type diffused layers formed at the same time as the base region (not shown) of the vertical npn transistor. Reference numerals 20 and 100 denote a collector and part of the emitter region, respectively, of the IIL, which are n-type diffused layers formed at the same time as the base region (not shown) of the vertical pnp transistor. Reference numeral 23 denotes a collector contact region of the IIL, which is an n.sup.+ -type diffused layer formed at the same time as the emitter region (not shown) of the vertical npn transistor.
In the conventional semiconductor device constituted in this way, the p.sup.- -type diffused layer 12 serving as the base of the IIL is a diffused layer with a low impurity density formed at the same time as the collector region of the vertical pnp transistor, and hence an emitter injection efficiency can be made higher and current gain can be made greater.
Other conventional semiconductor devices in which a highly integrated high-speed vertical npn transistor and an IIL are set up together are disclosed, for example, in Japanese Laid-open Patent Application No. 62-111461. FIG. 10 illustrates a cross section of the structure of this conventional semiconductor device.
In FIG. 10, reference numeral 1 denotes a p-type semiconductor substrate; and 5, part of the emitter region of the IIL, which is an n.sup.+ -type buried layer formed at the same time as a collector buried layer (not shown) of a vertical npn transistor. Reference numeral 9 denotes an n.sup.- -type epitaxial layer formed on the p-type semiconductor substrate 1. Reference numeral 301 denotes a groove formed at an emitter lead-out portion of the IIL; and 306, an n.sup.+ -type diffused layer that constitutes part of an emitter lead-out portion, formed by diffusing impurities from the bottom of the groove. Reference numeral 302 denotes an SiO.sub.2 film formed on the surface of the n.sup.- -type epitaxial layer 9. Reference numeral 303 denotes a p-type diffused layer serving as an injector of the IIL; 304, a p-type diffused layer serving as the base of the IIL; and 305, an n.sup.+ type diffused layer serving as a collector of the IIL.
In the conventional semiconductor device constituted in this way, the n.sup.+ -type diffused layer 306 is formed self-matchingly to the formation of the groove 301, and hence the emitter lead-out portion can be made narrower than in the case when an n.sup.+ -type diffused layer is formed at an emitter lead-out portion using a resist mask. Thus a semiconductor device in which a highly integrated high-speed vertical npn transistor and an IIL are set up together can be obtained.
However, in such conventional semiconductor devices, for example, the semiconductor device disclosed in Japanese Laid-open Patent Application No. 59-141261, the n-type diffused layer 100 is formed between the injector p-type diffused layer 17 and the emitter lead-out portion n-type diffused layer 14 and also between the base p-type diffused layer 18 and the separating region p-type diffused layer 10 so that breakdown voltage can be ensured between these diffused layers. Hence, this semiconductor device has had the problem that the cell size of the IIL is necessarily large. In addition, the presence of a parasitic capacitance between the regions formed by the n-type epitaxial layer 9 has brought about the problem that the operating speed of the IIL can not be increased with ease.
In the semiconductor device disclosed in Japanese Laid-open Patent Application No. 62-111461, the emitter lead-out portion of the IIL is formed of the groove 301 and the n.sup.+ -type diffused layer 306 located right beneath it, so that a difference in level may occur at this portion. Thus, this semiconductor device has been involved in the problem that disconnection or short of Al wiring tends to occur at this portion.